SK hynix & Samsung Validate 16-High HBM4 Memory Stacks: 4nm Base Dies Break 24 TB/s Barrier

The Three-Question Framework

What Happened?

SK hynix and Samsung Electronics both announced silicon validation and functional sample completion for 16-high High Bandwidth Memory 4 (HBM4) modules. Fabricated using a custom 4nm logic base die manufactured on TSMC N4P and Samsung Foundry 4nm processes respectively, the new 16-high stacks achieve 64GB per cube with a 2,048-bit wide memory interface. Utilizing copper-to-copper (Cu-Cu) hybrid bonding instead of traditional micro-bumps, the stacks achieve thermal resistance reductions of 33% and aggregate package bandwidth exceeding 24 Terabytes per second when configured in eight-cube accelerator modules.

Why It Matters

Memory bandwidth and capacity have become the definitive bottlenecks in frontier AI computing. As foundational models scale their context windows to millions of tokens and deploy continuous agent loops, GPU compute engines frequently stall while waiting for weights and KV caches to transfer from memory. The transition to a 2,048-bit interface on advanced 4nm logic dies doubles the interface width from HBM3E (1,024-bit), effectively shattering the bandwidth wall for NVIDIA's Rubin Ultra and AMD's Instinct MI400-series architectures.

What Could Happen Next

Engineering samples are being shipped to hyperscale accelerator designers including NVIDIA, Broadcom, and Google Cloud for validation on 2.5D/3D interposers, with commercial volume manufacturing slated to ramp in late Q1 2027.

Executive Key Takeaways

64 Gigabytes per cube: 16-high DRAM die stacking achieves the highest volumetric memory density in semiconductor history.

2,048-bit interface: double the bus width of HBM3E, delivering over 3.0 TB/s per cube and 24 TB/s per 8-cube accelerator.

Copper-to-copper (Cu-Cu) hybrid bonding: eliminates solder micro-bumps, slicing stack height to under 720 microns.

4nm custom logic base dies: allows near-memory compute filtering and specialized telemetry directly under the memory stack.

In a major milestone for semiconductor packaging, South Korea's premier memory manufacturers, SK hynix and Samsung Electronics, have achieved working silicon validation for 16-high HBM4 memory stacks. The breakthroughs demonstrate functional 64GB monolithic cubes that smash existing bandwidth and thermal barriers.

Since the advent of generative AI clusters, High Bandwidth Memory has been the lifeblood of accelerated compute. Yet the existing HBM3E standard, limited to 12-high stacks and a 1,024-bit bus width, has pushed conventional packaging physics to its absolute limit. With parasitic capacitance rising and thermal hotspots throttling GPU performance under continuous inferencing workloads, the industry recognized that standard micro-bump soldering could not survive another generation.

HBM4 fundamentally re-engineers the memory stack. Rather than using passive silicon base dies, both manufacturers transitioned to active custom 4nm logic dies. SK hynix partnered with TSMC to fabricate its base die on the N4P node, while Samsung leveraged its proprietary 4nm Gate-All-Around (GAA) process. By embedding logic circuits directly underneath the 16 DRAM layers, the base die handles high-speed signal routing, built-in self-test (BIST), and even localized near-memory data decompression.

The physical integration of 16 individual DRAM dies within the JEDEC-mandated package height constraint of 720 micrometers required the abandonment of micro-bump interconnects. Both companies deployed direct copper-to-copper (Cu-Cu) hybrid bonding. By polishing wafer surfaces to atomic smoothness and bonding copper pads directly without solder, the vertical interconnect pitch is reduced from 25 microns to less than 3 microns, yielding a 33% improvement in thermal dissipation.

The resulting performance metrics are staggering. Each 16-high HBM4 cube provides 64GB of capacity and operates at memory speeds of up to 3.2 Terabytes per second. When integrated into an AI accelerator housing an eight-cube memory ring, total system memory reaches 512GB with an aggregate memory bandwidth surpassing 24 Terabytes per seconda 300% bandwidth leap over current H200 and B200 systems.

As hyperscalers prepare for 2027 datacenter deployments, the silicon validation of 16-high HBM4 confirms that the physical memory wall is being held at bay, providing the prerequisite hardware platform for the next leap in trillion-parameter autonomous foundation models.

The Three-Question Framework

What Happened?

Why It Matters

What Could Happen Next

Executive Key Takeaways

Primary Sources & Citations