Cerebras CS-3 Wafer-Scale Engine Deploys 4 Trillion Transistors: Sustaining 1,800 Tokens/Sec on Frontier Models

The Three-Question Framework

What Happened?

Cerebras Systems began commercial deployment of its CS-3 Wafer Scale Engine, the largest single silicon chip ever created. Fabricated on TSMC's 5nm process node, the CS-3 packs 4 trillion transistors, 900,000 AI-optimized compute cores, and 44 Gigabytes of ultra-fast on-chip SRAM onto a continuous 46,225 mm² wafer, delivering 21 Petabytes per second of memory bandwidth and generating 1,800 tokens per second on 70B parameter models.

Why It Matters

Modern GPUs like Nvidia H100 and B200 are constrained in interactive inference by off-chip HBM memory bus bandwidth, capping single-stream output at 50 to 100 tokens per second. Because the CS-3 houses all active model weights directly in on-chip SRAM without external memory buses, it eliminates memory bottlenecks, enabling real-time spoken conversation and instantaneous code generation.

What Could Happen Next

Cerebras announced cloud API clusters hosted across North American datacenters, targeting agentic software engineering frameworks that require rapid multi-step reasoning loops.

Executive Key Takeaways

World's largest chip: 4 trillion transistors and 900,000 AI cores on a single 300mm wafer.

21 Petabytes/sec on-chip memory bandwidth: 8,000x faster than standard HBM3E GPU interfaces.

1,800 tokens/sec sustained throughput on Llama-3.1 70B, enabling imperceptible latency for human users.

Liquid-cooled architecture: dissipates 23 kW of heat using a custom copper cold-plate manifold.

On September 5, 2026, Cerebras Systems unveiled production benchmarks for its CS-3 Wafer Scale Engine, demonstrating sustained inference generation speeds exceeding 1,800 tokens per second on open-weights frontier models.

In modern AI architectures, token generation speed for a single user is strictly memory-bandwidth bound. Every generated token requires reading hundreds of billions of parameter weights from external High Bandwidth Memory (HBM) into compute registers. Even cutting-edge Nvidia Blackwell GPUs with 8 TB/s of memory bandwidth are limited to roughly 100 tokens per second for individual user streams.

Cerebras bypasses this architectural constraint by avoiding discrete packaged chips entirely. The CS-3 is etched across an entire 300mm silicon wafer as a single contiguous die. Because communication between all 900,000 cores occurs entirely on-wafer via a 2D mesh interconnect, memory bandwidth reaches 21 Petabytes per second—thousands of times greater than any discrete GPU cluster.

In production testing on Meta's Llama 3.1 70B model, the CS-3 achieved an instantaneous generation speed of 1,840 tokens per second with a time-to-first-token (TTFT) under 15 milliseconds. At this speed, an entire 20-page technical paper or a 500-line Python module generates in less than one-third of a second.

To support the massive chip, Cerebras engineers developed a specialized server enclosure utilizing closed-loop liquid cooling capable of extracting 23 kilowatts of thermal dissipation directly from the wafer surface.